Solar Energy Rejects: Silicon Wafers That Don’t Pass Muster

NREL-iconEditor’s Note: EarthTechling is proud to repost this article courtesy of the National Renewable Energy Laboratory. Author credit goes to Bill Scanlon.

Silicon wafers destined to become photovoltaic (PV) cells can take a bruising through assembly lines, as they are oxidized, annealed, purified, diffused, etched, and layered to reach their destinies as efficient converters of the sun’s rays into useful electricity.

All those refinements are too much for 5% to 10% of the costly wafers. They have micro-cracks left over from incomplete wafer preparation, which causes them to break on the conveyers or during cell fabrication.

NREL postdoctoral scientist Rene Rivero readies a wafer for the Silicon Photovoltaic Wafer Screening System.Credit: Dennis Schroeder

NREL postdoctoral scientist Rene Rivero readies a wafer for the Silicon Photovoltaic Wafer Screening System.
Image Credit: Dennis Schroeder

Scientists at the U.S. Department of Energy’s National Renewable Energy Laboratory (NREL) have developed an instrument that puts pressure on the wafers to find which ones are too fragile to make it through the manufacturing process — and then kicks out those weak wafers before they go through their costly enhancement. NREL’s Silicon Photovoltaic Wafer Screening System (SPWSS) is a cube-shaped furnace about 15 inches each side, and can be retrofitted into an assembly line.

The PV industry generated $82 billion in global revenues in 2010, producing 20.5 gigawatts of electricity from sunlight. Processing solar cells costs about 15 cents for each watt of potential energy, and the cells comprise about half the cost of an installed solar module. If a way can be found to eliminate the cost of the 5% to 10% of cells that are destined to fail before they’re finished, potential annual savings run into the billions of dollars.

It’s the kind of savings that can make the difference between a U.S. manufacturer winning or losing.

Wafer Screening System Simulates Manufacturing Stress

NREL’s Silicon Photovoltaic Wafer Screening System, developed by NREL scientist Bhushan Sopori with colleagues Prakash Basnyat and Peter Rupnowski, exposes a silicon wafer to thermal stress in the form of carefully calibrated high temperatures.

The process looks a lot like the toasting belt that turns a cold sub sandwich into a warm one. As each wafer passes through a narrow — 15-millimeter — high-intensity illumination zone, different strips of the wafer are exposed to the heat. That way, the stress travels through the wafer.

A PV wafer emerges from the Silicon Photovoltaic Wafer Screening System. This tool tests a pre-selection of wafers for high fracture strength, improving the yield of silicon solar cells by preventing breakage during cell fabrication. Image Credit: Dennis Schroeder

A PV wafer emerges from the Silicon Photovoltaic Wafer Screening System. This tool tests a pre-selection of wafers for high fracture strength, improving the yield of silicon solar cells by preventing breakage during cell fabrication.
Image Credit: Dennis Schroeder

“We create a very high temperature peak,” said Sopori, principal investigator for the SPWSS. “The idea is to create a thermal stress, like putting very hot water in a glass.”

The temperature can be calibrated precisely — most usefully by correlating it to the thickness of the wafer, because the thinner the wafer, the less stress it can withstand. Every manufacturer has different levels at which their wafers can break from stress, so the SPWSS can be calibrated precisely via computer to meet the needs of each solar cell maker.

The SPWSS is essentially a furnace shaped like a trapezoidal prism to narrow the focus of the light and increase its intensity. The ceramic sides of the furnace reflect the light to the intensity zone and ensure that almost no energy is wasted.

The lamps can be as hot as 1,800 degrees Celsius, but the hottest part of the wafer will feel about 500 degrees Celsius on its surface.

It’s the rapid increase in thermal energy — made possible by the geometry of the furnace and its highly reflective surfaces — that causes the stress. While one 15-millimeter strip of the wafer is feeling 500 degrees Celsius of stress, the strip adjacent to it feels much cooler. The hot strip wants to expand, but the cool strip doesn’t want any part of that. It’s these competing forces that cause the stress. “Every micron of the wafer sees this thermal stress,” Sopori said.

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